Obsidian

Description

Obsidian is a FPGA carrier board in development, designed to interface with ADC and DAC devices, either stand-alone or as an I/O expansion board for Marble.

The design files here were created with KiCad version 9.0.0-rc3.

Major Parts

• Xilinx Artix-7 XC7A35T FPGA
• 8 GB DDR3 RAM
• SPI 16 MB flash boot
• White Rabbit compatible
• 4 SFP ports (6.6 Gb/s)
• SMA external input clock
• 1 GigE port
• 6 Pmod ports
• Arduino shield compatible
• USB-C (data and PD)
• FTDI USB interface

Clock distribution

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    "fontSize": "16px",
    "lineColor": "#607d8b",
    "edgeLabelBackground": "#ffffff",
    "clusterBkg": "#ffffff",
    "clusterBorder": "#b0bec5"
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  "flowchart": { "curve": "basis", "nodeSpacing": 35, "rankSpacing": 70, "padding": 20 }
}}%%
flowchart LR

    %% ===================== SOURCES =====================
    subgraph SRC["Clock Sources"]
        direction TB
        Y2(["<b>Y2</b><br/>48 MHz"])
        J16(["<b>J16</b><br/>SMA ext. ref"])
        Y1(["<b>Y1</b><br/>25 MHz"])
    end

    %% ===================== JITTER CLEANER =====================
    U13{{"<b>U13</b><br/>Si5340B<br/>"}}

    %% ===================== CLOCK NETS =====================
    WR("<b>WR_CLK0</b><br/>LVDS")
    REF("<b>REF_CLK0</b><br/>LVDS")
    C20("<b>CLK20_VCXO</b><br/>20 MHz")
    C25("<b>CLK_25MHz</b><br/>25 MHz")
    CLK2("<b>CLK2</b><br/>25 MHz")

    %% ===================== FPGA =====================
    subgraph U1["<b>U1 Artix-7 XC7A35T</b>"]
        direction TB
        subgraph GTP["GTP Quad 216 (4x SFP)"]
            direction TB
            GTP0["<b>MGTREFCLK0</b><br/>D6 / D5"]
            GTP1["<b>MGTREFCLK1</b><br/>B6 / B5"]
        end
        SRCC["SRCC bank 15<br/>pin <b>D13</b>"]
        MRCC["MRCC bank 15<br/>pin <b>E15</b>"]
    end

    PHY[["<b>U7</b> RTL8211F<br/>Gigabit Ethernet PHY"]]

    %% ===================== CONNECTIONS =====================
    Y2  --> U13
    J16 --> U13
    U13 ==> WR
    U13 --> C25
    U13 --> C20
    U13 ==> REF
    WR  ==> GTP0
    REF ==> GTP1
    C20 --> SRCC
    C25 --> PHY
    Y1  --> CLK2
    CLK2 --> MRCC

    %% ===================== STYLES =====================
    classDef src  fill:#fff3e0,stroke:#ef6c00,stroke-width:2px,color:#bf360c
    classDef pll  fill:#6a1b9a,stroke:#38006b,stroke-width:3px,color:#ffffff
    classDef lvds fill:#f3e5f5,stroke:#8e24aa,stroke-width:2px,color:#4a148c
    classDef se   fill:#e3f2fd,stroke:#1e88e5,stroke-width:2px,color:#0d47a1
    classDef fpga fill:#ffffff,stroke:#2e7d32,stroke-width:2px,color:#1b5e20
    classDef ext  fill:#eceff1,stroke:#546e7a,stroke-width:2px,color:#263238

    class Y2,J16,Y1 src
    class U13 pll
    class WR,REF lvds
    class C20,C25,CLK2 se
    class GTP0,GTP1,SRCC,MRCC fpga
    class PHY ext

    style SRC fill:#fffaf3,stroke:#ffb74d,stroke-width:2px,stroke-dasharray:6 4,color:#e65100
    style U1  fill:#e8f5e9,stroke:#2e7d32,stroke-width:3px,color:#1b5e20
    style GTP fill:#c8e6c9,stroke:#43a047,stroke-width:2px,stroke-dasharray:5 5,color:#1b5e20

    linkStyle 0,1   stroke:#ef6c00,stroke-width:2px
    linkStyle 2,5,6,7 stroke:#8e24aa,stroke-width:3.5px
    linkStyle 3,4,8,9 stroke:#1e88e5,stroke-width:2px
    linkStyle 10,11 stroke:#ef6c00,stroke-width:2px

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Credits

License

The design is distributed under CERN-OHL-W-2.0 license.