Welcome to the home of Cal Poly's CARP, an ongoing group/club dedicated to open source chip design.
Many repositories in this organization rely on eachother, and use submodules to handle this. After cloning a repo, be sure to immediately initiate and update submodules:
git submodule init
git submodule update --recursive
All of these tools work best on Linux. Please refer to our Setup Instructions.
OSS Cad Suite bundles all of the necessary open source tools for digital design, inclduing:
- Verilator for Linting & Simulation
- CocoTB for Testing
- Yosys for Synthesis
- GTKWave for viewing waveforms
To install, follow the instructions here: https://github.com/YosysHQ/oss-cad-suite-build
In summary,
- Download the archive depending on your system here: https://github.com/YosysHQ/oss-cad-suite-build/releases/latest
- Extract it to somewhere accessible, such as your home directory
~ - Run the following command in EVERY terminal that needs OSS Cad Suite Tools:
source <extracted_location>/oss-cad-suite/environment
The RISC-V toolchain lets us compile C and Assembly files to get RISC-V machine code, as well as debug that code.
To install on Linux or WSL, follow the instructions here: https://github.com/stnolting/riscv-gcc-prebuilt
Example Installation on Linux:
wget https://github.com/stnolting/riscv-gcc-prebuilt/releases/download/rv32i-131023/riscv32-unknown-elf.gcc-13.2.0.tar.gz
sudo mkdir /opt/riscv
sudo tar -xzf riscv32-unknown-elf.gcc-13.2.0.tar.gz -C /opt/riscv/
echo "PATH=\$PATH:/opt/riscv/bin" >> ~/.bashrc
To install on Mac, follow these instructions: https://github.com/riscv-software-src/homebrew-riscv
