[Add] Parameterizable write gate and verification flows

.github/workflows/rtl-simulation.yml

@@ -143,12 +143,36 @@ jobs:
           set -o pipefail
           make MODULE="${{ matrix.module }}" PROFILE="${{ matrix.profile }}" OPENROAD_EXECUTION_MODE=container open-physical 2>&1 | tee ci-artifacts/native-openroad.log
 
+      - name: Run representative write-gate OpenROAD physical flow
+        if: matrix.module == 'write_gate' && matrix.profile == 'width_2'
+        run: |
+          set -o pipefail
+          make MODULE=write_gate PROFILE=width_2 FORCE_FLOW=1 \
+            OPENROAD_EXECUTION_MODE=container open-physical \
+            2>&1 | tee ci-artifacts/native-write-gate-openroad.log
+          openroad_dir=reports/write_gate/width_2/openroad
+          cp "${openroad_dir}/status.txt" "${openroad_dir}/forced-status.txt"
+          printf 'SKIP\n' > "${openroad_dir}/status.txt"
+
+      - name: Qualify write-gate functional and structural coverage
+        if: matrix.module == 'write_gate' && matrix.profile == 'width_2'
+        run: |
+          set -o pipefail
+          make MODULE=write_gate PROFILE=width_2 FORCE_FLOW=1 open-coverage \
+            2>&1 | tee ci-artifacts/native-write-gate-coverage.log
+          coverage_dir=reports/write_gate/width_2/coverage_qualification
+          cp "${coverage_dir}/status.txt" "${coverage_dir}/forced-status.txt"
+          printf 'SKIP\n' > "${coverage_dir}/status.txt"
+
       - name: Generate release evidence manifest
         env:
           MODULE_REVISION: ${{ github.sha }}
           METHODOLOGY_REVISION: ${{ steps.flow-revision.outputs.revision }}
         run: |
           set -o pipefail
+          if [[ "${{ matrix.module }}" == write_gate && "${{ matrix.profile }}" == width_2 ]]; then
+            export RELEASE_ADDITIONAL_EVIDENCE="reports/write_gate/width_2/coverage_qualification/forced-status.txt reports/write_gate/width_2/openroad/evidence.json reports/write_gate/width_2/openroad/forced-status.txt"
+          fi
           make MODULE="${{ matrix.module }}" PROFILE="${{ matrix.profile }}" release-manifest release-manifest-validate 2>&1 | tee ci-artifacts/native-release-manifest.log
 
       - name: Upload RTL reports
@@ -246,9 +270,42 @@ jobs:
             --env RELEASE_METHODOLOGY_DIRTY=false \
             --env RELEASE_EXECUTION_CONTEXT=container \
             --volume "${GITHUB_WORKSPACE}:/workspace" \
-            "mosaic-module-ci:${GITHUB_SHA}-${{ matrix.module }}-${{ matrix.profile }}" MODULE="${{ matrix.module }}" PROFILE="${{ matrix.profile }}" FLOW_openroad=disabled clean open-source release-manifest release-manifest-validate \
+            "mosaic-module-ci:${GITHUB_SHA}-${{ matrix.module }}-${{ matrix.profile }}" MODULE="${{ matrix.module }}" PROFILE="${{ matrix.profile }}" FLOW_openroad=disabled clean open-source \
             2>&1 | tee ci-artifacts/container-flow.log
 
+      - name: Qualify write-gate functional and structural coverage in container
+        if: matrix.module == 'write_gate' && matrix.profile == 'width_2'
+        run: |
+          set -o pipefail
+          docker run --rm \
+            --user "$(id -u):$(id -g)" \
+            --env HOME=/tmp \
+            --volume "${GITHUB_WORKSPACE}:/workspace" \
+            "mosaic-module-ci:${GITHUB_SHA}-${{ matrix.module }}-${{ matrix.profile }}" MODULE=write_gate PROFILE=width_2 FORCE_FLOW=1 open-coverage \
+            2>&1 | tee ci-artifacts/container-write-gate-coverage.log
+          coverage_dir=reports/write_gate/width_2/coverage_qualification
+          cp "${coverage_dir}/status.txt" "${coverage_dir}/forced-status.txt"
+          printf 'SKIP\n' > "${coverage_dir}/status.txt"
+
+      - name: Generate release evidence manifest in container
+        run: |
+          set -o pipefail
+          additional_evidence=""
+          if [[ "${{ matrix.module }}" == write_gate && "${{ matrix.profile }}" == width_2 ]]; then
+            additional_evidence="reports/write_gate/width_2/coverage_qualification/forced-status.txt"
+          fi
+          docker run --rm \
+            --user "$(id -u):$(id -g)" \
+            --env HOME=/tmp \
+            --env MODULE_REVISION="${GITHUB_SHA}" \
+            --env METHODOLOGY_REVISION="${{ steps.flow-revision.outputs.revision }}" \
+            --env RELEASE_ADDITIONAL_EVIDENCE="${additional_evidence}" \
+            --env RELEASE_METHODOLOGY_DIRTY=false \
+            --env RELEASE_EXECUTION_CONTEXT=container \
+            --volume "${GITHUB_WORKSPACE}:/workspace" \
+            "mosaic-module-ci:${GITHUB_SHA}-${{ matrix.module }}-${{ matrix.profile }}" MODULE="${{ matrix.module }}" PROFILE="${{ matrix.profile }}" FLOW_openroad=disabled release-manifest release-manifest-validate \
+            2>&1 | tee ci-artifacts/container-release-manifest.log
+
       - name: Upload container RTL reports
         if: always()
         uses: actions/upload-artifact@v7

README.md

@@ -18,6 +18,7 @@ repository infrastructure and pinned [`mosaic-flow`](mosaic-flow) methodology.
 | `level_shifter` | Technology-independent model of a unidirectional voltage-domain crossing | [`docs/level_shifter/`](docs/level_shifter/) |
 | `isolation_cell` | Parameterizable power-domain isolation and compile-time clamp behavior | [`docs/isolation_cell/`](docs/isolation_cell/) |
 | `retention_register` | Parameterizable visible state with explicit save and restore behavior | [`docs/retention_register/`](docs/retention_register/) |
+| `write_gate` | Parameterizable architectural suppression of per-bit write enables | [`docs/write_gate/`](docs/write_gate/) |
 
 The authoritative module list used by local automation and the GitHub Actions
 matrix is [`config/modules.json`](config/modules.json). Parameterized modules

config/coverage-policies/write_gate.json

@@ -0,0 +1,54 @@
+{
+    "schema": "mosaic-coverage-policy-v1",
+    "scope": {
+        "include": [
+            "rtl/write_gate.sv",
+            "verif/coverage/write_gate_coverage.sv",
+            "verif/coverage/write_gate_transition_coverage.sv",
+            "verif/coverage/write_gate_integration_coverage.sv"
+        ],
+        "exclude": []
+    },
+    "thresholds": {
+        "line": 100,
+        "branch": 100,
+        "toggle": 90,
+        "user": 100
+    },
+    "coverpoints": [
+        {"name": "truth_00", "minimum_hits": 1},
+        {"name": "truth_01", "minimum_hits": 1},
+        {"name": "truth_10", "minimum_hits": 1},
+        {"name": "truth_11", "minimum_hits": 1},
+        {"name": "every_bit_permitted", "minimum_hits": 1},
+        {"name": "every_bit_suppressed", "minimum_hits": 1},
+        {"name": "zero_suppression_ratio", "minimum_hits": 1},
+        {"name": "partial_suppression_ratio", "minimum_hits": 1},
+        {"name": "complete_suppression_ratio", "minimum_hits": 1},
+        {"name": "partition_observed", "minimum_hits": 1},
+        {"name": "mixed_write_decision", "minimum_hits": 1},
+        {"name": "transition_00_00", "minimum_hits": 1},
+        {"name": "transition_00_01", "minimum_hits": 1},
+        {"name": "transition_00_10", "minimum_hits": 1},
+        {"name": "transition_00_11", "minimum_hits": 1},
+        {"name": "transition_01_00", "minimum_hits": 1},
+        {"name": "transition_01_01", "minimum_hits": 1},
+        {"name": "transition_01_10", "minimum_hits": 1},
+        {"name": "transition_01_11", "minimum_hits": 1},
+        {"name": "transition_10_00", "minimum_hits": 1},
+        {"name": "transition_10_01", "minimum_hits": 1},
+        {"name": "transition_10_10", "minimum_hits": 1},
+        {"name": "transition_10_11", "minimum_hits": 1},
+        {"name": "transition_11_00", "minimum_hits": 1},
+        {"name": "transition_11_01", "minimum_hits": 1},
+        {"name": "transition_11_10", "minimum_hits": 1},
+        {"name": "transition_11_11", "minimum_hits": 1},
+        {"name": "protocol_idle_no_decision", "minimum_hits": 1},
+        {"name": "protocol_accepted_permit", "minimum_hits": 1},
+        {"name": "protocol_accepted_suppress", "minimum_hits": 1},
+        {"name": "register_redundant_suppression", "minimum_hits": 1},
+        {"name": "memory_redundant_suppression", "minimum_hits": 1}
+    ],
+    "exclusions": [],
+    "formal": {"required": true}
+}

config/modules.json

@@ -9,6 +9,7 @@
         {"name": "priority_encoder"},
         {"name": "level_shifter"},
         {"name": "isolation_cell"},
-        {"name": "retention_register"}
+        {"name": "retention_register"},
+        {"name": "write_gate"}
     ]
 }

config/modules/write_gate-flows.mk

@@ -0,0 +1,36 @@
+# Required portable checks for the technology-independent write-control leaf.
+FLOW_verible_lint := enabled
+FLOW_verible_format := enabled
+FLOW_slang_elaboration := enabled
+FLOW_verilator_lint := enabled
+FLOW_yosys_synthesis := enabled
+FLOW_symbiyosys_formal := enabled
+FLOW_eqy_equivalence := enabled
+FLOW_verilator_sim := enabled
+FLOW_coverage_qualification := enabled
+FLOW_negative_qualification := enabled
+FLOW_four_state_qualification := enabled
+FLOW_static_intent := enabled
+
+# Technology, destination timing, domains, scan, and activity belong to the
+# first stateful integration that consumes the write enable.
+FLOW_openroad := disabled
+FLOW_vcs_sim := disabled
+FLOW_pyuvm_open_source := disabled
+FLOW_pyuvm_commercial := disabled
+FLOW_vc_lint := disabled
+FLOW_vc_cdc := disabled
+FLOW_sg_cdc := disabled
+FLOW_sg_dft := disabled
+FLOW_vc_lp := disabled
+FLOW_synopsys_synthesis := disabled
+FLOW_synopsys_primetime := disabled
+FLOW_synopsys_primepower := disabled
+
+FLOW_DEPENDENCIES_eqy_equivalence := yosys_synthesis
+FLOW_DEPENDENCIES_coverage_qualification := verilator_sim
+FLOW_DEPENDENCIES_negative_qualification :=
+FLOW_DEPENDENCIES_four_state_qualification :=
+FLOW_DEPENDENCIES_static_intent :=
+FLOW_DEPENDENCIES_synopsys_primetime :=
+FLOW_DEPENDENCIES_synopsys_primepower :=

config/modules/write_gate.mk

@@ -0,0 +1,59 @@
+# Write-gate tops and design-owned flow inputs.
+export DESIGN_TOP := write_gate
+export TB_TOP := $(DESIGN_TOP)_tb
+export FORMAL_TOP := $(DESIGN_TOP)_formal
+export DUT_INSTANCE := $(TB_TOP)/u_unit/dut
+
+export FLOW_CONFIG_ROOT := $(MODULE_ROOT)/flows
+export RTL_FILELIST := $(call resolve_filelist,rtl.f)
+export TB_FILELIST := $(call resolve_filelist,tb.f)
+export FORMAL_FILELIST := $(call resolve_filelist,formal.f)
+export PROPERTY_FILELIST := $(call resolve_filelist,properties.f)
+export ASSERTION_FILELIST := $(call resolve_filelist,assertions.f)
+export COVERAGE_FILELIST := $(call resolve_filelist,coverage.f)
+export VERILATOR_WAIVER_FILE := $(FLOW_CONFIG_ROOT)/verilator_lint/waivers.vlt
+export VERIBLE_WAIVER_FILE := $(FLOW_CONFIG_ROOT)/verible/waivers.txt
+export VERIBLE_RULES_FILE := $(FLOW_CONFIG_ROOT)/verible/rules
+export VERIBLE_FORMAT_ARGS := --indentation_spaces=4
+export VERIBLE_FORMAT_PATHS := \
+    rtl/write_gate.sv \
+    verif/properties/write_gate_predicates.svh \
+    verif/assertions/write_gate_sva.sv \
+    verif/assertions/write_gate_bind.sv \
+    verif/coverage/write_gate_coverage.sv \
+    verif/coverage/write_gate_transition_coverage.sv \
+    verif/coverage/write_gate_integration_coverage.sv \
+    verif/coverage/write_gate_coverage_bind.sv \
+    verif/formal/write_gate_integration_formal.sv \
+    verif/formal/write_gate_formal.sv \
+    verif/mutations/write_gate_inverted_suppress_mutant.sv \
+    verif/tb/write_gate_test_case.sv \
+    verif/tb/write_gate_integration_test_case.sv \
+    verif/tb/write_gate_tb.sv \
+    verif/tb/write_gate_four_state_tb.sv \
+    verif/tb/write_gate_invalid_width_tb.sv
+export FORMAL_CONFIG := $(call resolve_flow_config,symbiyosys,formal.sby)
+export FORMAL_COVER_CONFIG := $(MODULE_ROOT)/flows/symbiyosys/write_gate.cover.sby
+export EQUIVALENCE_CONFIG := $(call resolve_flow_config,eqy,equivalence.eqy)
+export COVERAGE_QUALIFICATION_POLICY := $(MODULE_ROOT)/config/coverage-policies/write_gate.json
+export COVERAGE_QUALIFICATION_SOURCE := verilator_sim
+export SIM_COVERAGE := enabled
+export QUALIFICATION_CAMPAIGN_MANIFEST := $(MODULE_ROOT)/config/qualification-campaigns/write_gate.json
+export STATIC_INTENT_CONFIG := $(MODULE_ROOT)/config/static-intent/write_gate.json
+export OPENROAD_CONFIG := $(call resolve_flow_config,openroad,config.mk)
+export SYNTHESIS_CONSTRAINT_FILE := $(call resolve_flow_config,synthesis,timing.sdc)
+export ASYNC_SYNTHESIS_CONSTRAINT_FILE :=
+export OPENROAD_CONSTRAINT_FILE := $(MODULE_ROOT)/flows/openroad/write_gate.timing.sdc
+export CDC_CONFIG := $(call resolve_flow_config,cdc,constraints.tcl)
+export DFT_CONFIG := $(call resolve_flow_config,sg_dft,constraints.tcl)
+export UPF_CONFIG := $(call resolve_flow_config,vc_lp,power.upf)
+export CONSTRAINT_DIR := $(FLOW_CONFIG_ROOT)/synthesis
+
+export REPORT_DIR := $(MODULE_ROOT)/reports/$(MODULE)
+export WORK_DIR := $(MODULE_ROOT)/work/$(MODULE)
+export OPENROAD_PLATFORM ?= nangate45
+export TECH_SETUP_TCL ?=
+export TARGET_LIBRARY ?=
+export LINK_LIBRARY ?=
+export OPERATING_CONDITION ?=
+export ACTIVITY_FILE ?=$(WORK_DIR)/vcs_sim/$(DESIGN_TOP).saif

config/parameter-profiles/write_gate.json

@@ -0,0 +1,53 @@
+{
+    "schema": "mosaic-parameter-profiles-v1",
+    "include": [
+        {
+            "name": "width_1",
+            "parameters": {"WIDTH": 1},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "negative_qualification", "four_state_qualification", "static_intent"],
+            "tops": {"design": "write_gate", "testbench": "write_gate_tb", "formal": "write_gate_formal"}
+        },
+        {
+            "name": "width_2",
+            "parameters": {"WIDTH": 2},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "write_gate", "testbench": "write_gate_tb", "formal": "write_gate_formal"}
+        },
+        {
+            "name": "width_4",
+            "parameters": {"WIDTH": 4},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "write_gate", "testbench": "write_gate_tb", "formal": "write_gate_formal"}
+        },
+        {
+            "name": "width_8",
+            "parameters": {"WIDTH": 8},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "write_gate", "testbench": "write_gate_tb", "formal": "write_gate_formal"}
+        },
+        {
+            "name": "width_16",
+            "parameters": {"WIDTH": 16},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "write_gate", "testbench": "write_gate_tb", "formal": "write_gate_formal"}
+        },
+        {
+            "name": "width_32",
+            "parameters": {"WIDTH": 32},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "write_gate", "testbench": "write_gate_tb", "formal": "write_gate_formal"}
+        },
+        {
+            "name": "width_64",
+            "parameters": {"WIDTH": 64},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "write_gate", "testbench": "write_gate_tb", "formal": "write_gate_formal"}
+        },
+        {
+            "name": "width_128",
+            "parameters": {"WIDTH": 128},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "write_gate", "testbench": "write_gate_tb", "formal": "write_gate_formal"}
+        }
+    ]
+}