Complete eSim 2.6 modernization with a new UI, HDL workflows, and installers

[VaradhaCodes]

eSim 2.6

This PR brings the eSim desktop application, simulation workflows, and release tooling together as one modernized 2.6 release. It introduces a new PyQt6 workspace, a proper project editor, rebuilt model and subcircuit tools, integrated Verilog and VHDL flows, mixed-signal waveform support, direct KiCad 7 to 10 conversion, and native delivery paths for Ubuntu and Windows.

Light mode	Dark mode

A new application workspace

The interface now follows one visual and interaction system across the welcome page, project explorer, editors, docks, dialogs, waveform windows, and engineering tools. Aurora supports live light and dark themes, screen-aware scaling, persistent zoom, clearer tooltips, consistent icons, resizable workspaces, fullscreen tools, and reliable window ownership.

Projects no longer feel like a collection of separate popups. Source files, generated files, models, simulation output, snapshots, and tools remain attached to the project that owns them.

Project workspace	Integrated source editor

The editor adds syntax highlighting, find and replace, line numbers, wrapping, whitespace controls, external-change detection, and draggable tabs for SPICE, Verilog, VHDL, Python, JSON, Markdown, and plain-text project files.

Subcircuits and device models rebuilt

Two of eSim's oldest utilities are now first-class project tools instead of small modal forms.

Subcircuit Builder

Previous interface	eSim 2.6

The new builder makes the source, symbol, model, and output paths visible in one place. It understands modern KiCad projects, keeps the legacy circuit fallback, validates the selected target before conversion, and prevents overlapping conversion jobs from corrupting generated output.

Model Editor

Previous interface	eSim 2.6

The Model Editor now uses an expanding parameter table, clearer model categories, searchable device definitions, explicit save state, and project-aware model paths. Large models are readable without squeezing every parameter into a fixed dialog.

HDL from source to waveform

Maker now connects HDL authoring, verification, model generation, placement, and simulation inside eSim. Each stage passes an explicit source revision, diagnostics, generated model, and waveform forward, so the result belongs to the design the user actually ran.

Author and build	Verify inside eSim

The workflow includes:

• Verilog compilation and functional verification with Icarus Verilog
• diagnostics mapped back to the relevant source line
• VCD parsing and an integrated digital waveform viewer
• NgVeri model generation through Verilator
• NGHDL model generation through GHDL and ngspice
• Makerchip integration through an isolated local session bridge
• atomic symbol-library updates and exact model removal

Mixed-signal simulation that stays understandable

The d_cosim, NgVeri, and NGHDL paths now converge on the same project and plotting model. Analog and digital traces retain their full names, multiple digital blocks can coexist in one design, and generated simulator state is kept separate for each backend.

The plotting workspace was also decomposed into dedicated data, trace, rendering, cursor, pane, palette, and expression layers. Normal, stacked, timing, and X-Y plots now share the same trace model. Large results use bounded drawing without reducing the full-resolution data used for cursors, measurements, or statistics.

KiCad 7 to 10 conversion

eSim no longer depends on the legacy KiCad SPICE exporter that disappeared from newer releases. A direct schematic netlister now reads modern KiCad schematics and produces the simulation input while preserving node order, model fields, subcircuit identity, and mixed-signal blocks.

The converter keeps the last usable circuit when a new conversion fails, reports the rejected boundary clearly, and supports migrated projects without silently choosing an obsolete schematic beside the current one.

Ubuntu and Windows delivery

The repository now contains the complete installation and release path for both supported platforms.

Ubuntu installer	Windows installer	Toolchain doctor

Ubuntu

• one profile-driven installer for supported Ubuntu releases through 26.04
• dry-run, progress display, logging, doctor, uninstall, and legacy cleanup modes
• installation of ngspice 45.2, GHDL, Verilator, Icarus Verilog, NGHDL, and required patches
• a release workflow that builds the Linux zip from the selected Git revision and publishes its SHA-256 checksum
• a clean archive gate that rejects development-only files, generated simulator output, and incomplete payloads

Windows

• a native Inno Setup installer built entirely from repository scripts
• private Python runtime and pruned KiCad payload
• ngspice, Icarus, GHDL, Verilator, NGHDL, and required runtime libraries
• per-user configuration, shortcuts, logs, repairable bootstrap, clean uninstall, and SKY130 support

Maintainers and contributors can build the same deliverables from the checked-out source:

./make-release.sh

pwsh -ExecutionPolicy Bypass -File windows/build-windows.ps1

What changed under the interface

• application paths, preferences, dialogs, and tool discovery now have shared owners
• simulator and converter jobs have bounded lifetimes, cancellation, and output gates
• project files and generated libraries use atomic writes where partial output would be destructive
• the toolchain doctor checks actual capabilities, not only executable names or version strings
• packaging is generated from the selected Git revision and excludes caches, local builds, and repository administration files
• the completed work spans 412 files and is presented as eleven reviewable release slices

This is the completed eSim modernization work from the 2026 FOSSEE Summer Fellowship at IIT Bombay.

Read the full implementation report