[carlosqwqqwq]

csr: validate CSRRS/CSRRC writes by register index

Fixes #293

Commit message

csr: validate CSRRS/CSRRC writes by register index

Description

The CSR helper decides whether CSRRS/CSRRC writes from the runtime value loaded from rs1. A nonzero rs1 register containing zero is therefore mistakenly treated as a read, allowing writes to read-only time. Carry the architectural write-intent bit from the decoder into the helper: only rs1=x0/zimm=0 forms are read-only accesses.

The write-intent bit now also reaches the shared riscv_csr_topei() AIA path; it no longer reconstructs intent from the source value and operation code.

Validation

• Native RISC-V hardware and QEMU trap csrrs/csrrc with rs1 = t0 (value zero) against read-only time and accept only the canonical rs1 = x0 read form; the patched build matches both.

The revised patch was applied to current staging and rebuilt with -Werror. The write-form witness traps in both RVVM execution modes with the expected illegal-instruction cause and CSR instruction tval; the canonical rs1=x0 read form remains covered by the existing reference witness.

[LekKit]

The riscv_csr_topei() helper still uses riscv_is_csr_write() instead of the write argument. This should be fixed, then riscv_is_csr_write() can be dropped as its sole caller is gone. Also worth renaming write -> is_write because it collides with a POSIX function name otherwise.