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perf(codegen): array families in one SCC pass; Fx hashing for the analysis maps - #12791
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…lysis maps array_families::collect propagated each property write on its own through the whole-module flow graph (a work-list per write into HashMap<Node, BTreeSet>, nodes holding owned field names, SipHash). On tsc that was ~8 s per call; codegen calls it twice per module (the births pre-pass and the compile), and it held 71% of the SipHash samples of the serial phases. The flow graph now interns its nodes as u32 (field names borrowed from the HIR) and keeps its edges in one array. Each propagation (call targets, then write keys) is one pass over the strongly connected components in topological order: a component's sorted item set is complete once every component reaching it is done, and it merges into each successor component once. Only the births' and callees' sets are kept. Same facts, same key order (first write first), same descriptor names: on tsc, zod, fastify and effect every module's layouts and births matched the previous algorithm, and the linked binaries are byte-identical. The Fx hasher moves from perry_wpfacts::pts to perry_hir::fx (wpfacts re-exports it) so codegen can use it; layout_families::late's maps use it. Their iteration order never reaches output: the binaries are identical, and a base compiled twice is identical to itself. tsc (tscwork, qb8): births pre-pass 9.8-11.9 s -> 2.4 s, class dispatch and representation analysis 11.3-13.8 s -> 3.4 s.
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tsc compile (tscwork), qb8, base c081ed7 vs head, interleaved n=3, taskset 0-13, host load 17-49 (shared host; instructions:u is the primary number):
The remaining serial lowering is the closure-body stage (~55 s), the next item in the compile-speed plan. |
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array_families::collectpropagated each property write separately through the module's flow graph: a work-list per write intoHashMap<Node, BTreeSet<usize>>, with nodes holding owned field names and SipHash on every step. On tsc it took ~8 s per call, and codegen calls it twice per module (births pre-pass + compile). In a frame-pointer profile of a tsc compile it held 71% of the SipHash samples of the serial phases.Change (no behavior change)
u32(field names borrowed from the HIR); edges live in one array.perry_wpfacts::ptstoperry_hir::fx(wpfacts re-exports it);layout_families::lateuses it (its next-largest SipHash user, lookups only).Verification (qb8, base = c081ed7)
-p perry-codegen --lib layout(75 tests).tsc compile phases (tscwork): births pre-pass 9.8–11.9 s → 2.4 s; class dispatch and representation analysis 11.3–13.8 s → 3.4 s. Interleaved n=3 instructions:u / task-clock in a follow-up comment.
Found while doing this (fixed in a follow-up PR): the address-keyed
BIRTH_LAYOUTStable misses every birth inside a closure, becausecollectors/closures.rslowers closure bodies from deep clones — on tsc 606 births are assigned and 0 hit. The follow-up moves the layout onto the HIR birth and deletes the table.