Improve MIPS floating-point lifting and calling conventions - #8500
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Decode floating-point memory operands correctly and lift lwc1, swc1, ldc1, and sdc1 using the appropriate FPR representation. Model MIPS32 FR=0 doublewords as register pairs and mark odd pair roots unknown. Add lifting tests across endianness, MIPS64, and R5900.
Lift MFC1, MTC1, DMFC1, DMTC1, MFHC1, and MTHC1 directly where supported by the modeled FPR layout. Preserve known low-word dataflow for MTC1 while modeling the unpredictable upper word, handle FR=0 register pairs, and add variant lifting tests.
Implement the remaining C.cond.S, C.cond.D, and C.cond.PS predicates, including unordered comparisons, explicit FCC destinations, FR=0 double pairs, and paired-single lane results.
Add MADD.S/D lifting, use a compact intrinsic for MADD.PS, and lifting integer and floating-point MOVF/MOVT variants with correct FCC polarity. Handle FR=0 double pairs, FR=1 registers, unpredictable operand combinations, and add regression coverage.
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This PR includes the following:
test_lifting.py) for fixed and newly lifted instructionsCloses #4010
After/Before:
