MSc student in High Performance Computing · Systems & Computer Architecture
📍 Barcelona, Spain · 🎓 MIRI-HPC @ Universitat Politècnica de Catalunya (UPC)

I'm a computer engineer (BSc, Universitat Politècnica de València) currently studying the Master in Innovation and Research in Informatics (MIRI), specializing in High Performance Computing, at UPC. I like to understand how systems work under the hood, and I'm especially interested in low-level programming, parallel computing, operating systems, and computer architecture, and I enjoy building efficient, robust, hardware-aware software.

This is where I share personal projects, experiments, and tools as I keep growing as an engineer.

• ⚡ High Performance Computing: parallel programming, performance analysis, and getting the most out of the hardware
• 🖥️ Operating Systems & Performance: how the kernel, scheduler, and memory hierarchy shape real workloads
• 🔩 Computer Architecture: memory management units, RISC-V, and hardware verification
• 🧮 Data Structures & Algorithms: competitive programming and problem solving

A pipelined RISC-V CPU written in SystemVerilog: a 5-stage datapath with caches, a reorder buffer, a store buffer and a pipelined integer multiplier. It's simulated with Verilator and tested with bare-metal C programs (Fibonacci, BST, matrix multiply).

The drone module of Oroneta, a system for managing autonomous drones for monitoring, surveillance and emergency response. Written in C++, it provides the drone's API, a manager that handles its movements and tasks, and an AI component that processes the collected data.

Also: SystemVerilog for hardware design and verification.

🌱 Currently learning (HPC):

📬 Feel free to reach out if you're into systems, performance, or just love digging into how computers really work.