Repository navigation
drm: apple: isolate an experimental T8140 external display profile - #278
Merged
Merged
Conversation
Add a separate external H17P method profile and compact service serializer for bounded trials. Keep the existing internal H17P send rejection and boot-mode inheritance unchanged. Restrict the new serializer to the existing DisplayPort and EDID service calls, validate ring occupancy, and reject unknown callbacks without fabricating success. The compact transmit header and existing command descriptor are protocol hypotheses derived from public interfaces. No hardware compatibility is claimed. This commit does not enable or match an external controller. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Add a default-off T8140 external-controller experiment. Require the inherited START, STOPPED and IDLE state before the standard start/wake path and pin its DMA lifetime before any startup write. Complete this optional preparation during platform probe so failed or deferred controllers do not become prerequisites for the internal DRM master. Only successfully bound, prepared controllers are included. Preserve started-session mappings on failure and quiesce retained external work during shutdown. Internal H17P lifecycle remains unchanged. Hardware qualification and validated external resource mappings remain required before this experiment can be used as a supported display path. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The optional external error path referenced a retrain work item absent from this source base. Use dcp_disable_typec_work(), which already blocks and drains both existing Type-C work items. Preserve the initial compilation failure for review. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Describe the external display controller and four display apertures plus its fifth clock aperture from bounded read-only ADT observations. Select the first observed DCP mapper and the observed PIODMA stream. Add the reciprocal rear Type-C graph while retaining disabled controller and route status. Register names follow existing public bindings. Mailbox, firmware handoff, routing and bandwidth integration remain qualification requirements. This resource description is not a display readiness claim. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Use the generic DCP fallback required by the published T8140 external binding and explicitly classify that specific compatible as an external pipeline. Otherwise the display master never discovers a successfully prepared external node. The device and route remain disabled by default. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Keep the external CPU supply on after the loader validates and publishes its power-domain chain. The supply remains disabled in the static tree, so a refused handoff does not register or power it. This preserves firmware ownership while allowing mailbox consumers to bind. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Separate the number of display windows from the shared firmware clock aperture. Preserve the internal five-window profile and validate the external four-window profile against its existing final clock resource. Require explicit read-only experimental bandwidth offsets for the external profile, with alignment, distinctness and aperture bounds checks before startup. Keep both offsets unset by default and reject missing external clock rates rather than guessing them. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Describe the rear Type-C route and both scanout DARTs in a separate test DTB. Keep the normal J700 tree unchanged. The external DART must be withdrawn by the paired loader when external validation fails. Route selectors and external bandwidth parameters still require hardware qualification. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Report which bounded startup wait failed so endpoint discovery, host readiness and IOP acknowledgment failures can be distinguished without logging message payloads. Successful handshakes remain unchanged. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The external H17P trial completes endpoint setup but its normal RTKit wake sequence times out. Use the existing early-AP wake helper for this experimental profile, which announces host readiness before waiting for IOP readiness. Keep the normal wake sequence for other profiles. This ordering is a hardware qualification candidate. The previous trial retained the internal panel but did not expose an external connector. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The external H17P startup requests a shared buffer at a firmware-provided IOVA. Its setup callback maps that buffer, but the standard RTKit ops do not acknowledge mapped buffers. Select the existing co-processor-owned buffer protocol for this experimental profile so RTKit acknowledges the request and starts the crashlog endpoint before its endpoint-map reply. Keep other display profiles on their existing ops. Restore the normal wake ordering after the earlier AP-readiness trial also timed out, while retaining diagnostics for subsequent qualification. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The early-AP trial still lacked acknowledgments for firmware-owned shared buffers. The buffer-protocol trial supplied those acknowledgments but kept waiting for IOP readiness before announcing AP readiness. Neither trial established that one change alone could complete the external handshake. Combine the existing early-AP helper with the corrected buffer protocol for the experimental external profile. Keep normal display profiles and all timeout and lifetime rules unchanged. Hardware qualification of the combined sequence remains required. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The internal display DART already describes a 1 TiB-based, 64 GiB DMA window. The external trial omitted that range, so its shared buffer was allocated below the firmware window while the internal controller used the high window and completed its power handshake. Describe the same window on the external DART in the test tree. This matches the high address of the external firmware-owned buffer observed during startup. Leave the normal J700 tree unchanged. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The external H17P firmware announces dispext-service on the existing IBOOT endpoint. Match that measured service name for the experimental external profile, keeping the normal disp0-service table unchanged. Propagate endpoint allocation and startup failures to the caller. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Report external-profile control-message types and ring readiness when startup times out. Exclude normal receive notifications and rate-limit control diagnostics; no payload contents or addresses are logged. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
External H17P reaches AFK transport readiness but does not announce the DPTX port service. Its existing allocator endpoint is currently started only later with IOMFB. Make that known endpoint available before external service discovery, and skip its duplicate start during IOMFB startup. Keep normal H17P ordering unchanged. This external-only ordering change requires hardware validation; no new endpoint or message is introduced. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Limit external AFK control diagnostics to DPTX so unrelated endpoint startup cannot consume their rate limit. Distinguish a ready transport with no announced port service from a transport-start timeout. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The public m1n1 display startup initializes the DPTX controller endpoint before the port endpoint. Add that existing AFK controller interface to the experimental external H17P path, wait for its service announcement, and then continue port discovery. Send no controller service commands. Use a dedicated endpoint pointer and route its incoming messages through the existing AFK worker. Cover both retained-session quiescing and normal teardown, and never publish an allocation error as an endpoint pointer. Normal display profiles retain their existing startup sequence. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The external H17P test reaches transport readiness on the legacy DPTX endpoint without receiving a port announcement. The public version-two firmware implementation uses endpoint 0x2c, which this firmware advertises. Use that endpoint for an isolated service-discovery test. Keep a separate endpoint object with an initialization-only service table, RX routing and lifecycle handling. This does not enable operational port callbacks or transmit service commands; the discovered identity and framing must be validated before extending the command path. Normal profiles retain the legacy DPTX endpoint. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The external T8140 controller announces its port on endpoint 0x2c using version-two frames. Select that transport per endpoint, open announced interfaces and map the single physical DCP unit to logical port zero. Encode bounded command descriptors and validate replies against pending owned buffers before completing them. Preserve callback tokens and limit peer-buffer access to active allocations of the same service. Keep the legacy transport for other display profiles. Add host selftests for frame encoding, malformed records, response correlation, command identifiers and the production owned-copy helper. These pass 905 codec assertions and owned-copy cases with sanitizers; hardware qualification of the operational transport remains pending. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Document the three bounded calibration lists used for T8140 DisplayPort setup. Describe their register regions and ordering, and reject these properties on other PHY variants. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The T8140 variant currently returns from AUX setup without configuring it. The bootloader supplies three ordered DisplayPort setup lists, but the PHY driver does not read or apply them. Validate every list against its mapped register resource and apply the complete bundle at AUX setup. Reject DP selection if the bundle is missing or invalid, while keeping ordinary USB operation independent. Other PHY generations keep their existing setup paths. Drive-level training programming remains unchanged. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The experimental external profile uses AFKV2 for its DPTX port, but the companion controller endpoint still uses the legacy path. Its interfaces are discovered without receiving the version-two OPEN handshake. Select AFKV2 for the controller before starting it, so controller publication performs the same OPEN-before-ready sequence as the port. Add a one-time PHY setup message to distinguish successful calibration application from controller activation during hardware qualification. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
A DisplayPort mode can reach the display route without the PHY setup function being called. Add default-off dynamic-debug messages for each mux callback result and for the ATC requested, current and target modes. This distinguishes callback dispatch, unavailable setup data and an unchanged PHY mode without accessing additional hardware registers. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Add an explicit read-only diagnostic for the exact words selected by the T8140 DisplayPort setup lists. Validate the machine, mapped resource layout, list alignment and every offset before opening the memory device. Compose overlapping writes and report only mismatching masks and offsets, without exposing calibration values or writing registers. Four hardware-independent tests cover write composition, separate resources and malformed or out-of-range lists. Hardware readback remains an observation rather than a display qualification result. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Use a page-aligned read-only mapping for each selected MMIO word. The memory-device read syscall does not provide the device mapping required by this target. Preserve exact resource and offset admission and never create a writable mapping. Test the same mapped-word reader against a temporary file, including its alignment refusal, alongside the existing setup-list composition tests. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Report the analog shutdown, supply override and clamp control bits beside the setup-list readback. Keep the read-only resource checks and avoid printing complete register values or calibration data. Add a decoder test covering asserted and cleared states. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
J700 reaches DisplayPort mode with its setup-list values present, but readback shows AUX still clamped and both supply overrides unset. The calibration lists do not perform the AUX power transition. Request the small and large supplies in order, release the clamp, then release analog shutdown. Check each masked state with a bounded poll. Track incomplete startup so a later shutdown can unwind it, and refuse to stop the domain if AUX cleanup fails. Leave ordinary USB operation and other PHY generations on their existing paths. Add host tests of the production transition helpers with register mocks, covering phase ordering, unrelated bits and failure at every stage. These pass with AddressSanitizer and UBSan; hardware qualification is pending. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Extend the read-only state report with both lane protocol selections, power-control nibbles and receive override bits. Keep the fixed resource admission and add a synthetic two-lane decoding test. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The selected DP lane still reports the active power-control nibble after its protocol changes, with both receive overrides clear. The J700 path requires this lane to reach its quiescent state before link training. Assert only the selected lane's receive overrides, then sequence its power-control field into idle with bounded readback checks. Preserve the USB lane and unrelated bits. Return failures to the mux caller instead of publishing a completed mode transition. Host tests of the production helpers cover both lanes, invalid indices, unrelated-bit preservation and a failed write at every phase, under AddressSanitizer and UBSan. Hardware qualification remains pending. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Route the test connector to dispext1,0, matching its external DCP index. The selector denotes the crossbar source and is independent of physical Type-C port zero. Hardware routing facts were audited with user authorization; this DT change is independently written. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Document the firmware-provided fallback and per-rate drive tables. Each has sixteen entries indexed by voltage swing and pre-emphasis; other PHYs do not accept these properties. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
After correcting the crossbar route, J700 reaches SET_LINK_RATE but the legacy PHY path waits for the wrong command-ready register. Add an isolated T8140 main-link sequence, firmware drive presets, and cleanup ownership that survives failed setup or shutdown. Preserve the other PMA used for USB. Handle the version-two group-one drive command with complete bounds and range checks before changing the PHY. Cache training values only after a successful PHY operation and retain the legacy endpoint behavior. Hardware register facts were audited with explicit user authorization. The implementation and tests are independently written. The copy audit matched only three hardware-field expressions and standard C test headers. No private implementation patch was applied. Validation: 29 PHY state scenarios, 112 callback boundary cases, 100 group routing cases, 905 AFK assertions and production owned-buffer/AUX tests under ASan/UBSan; schema validation and strict checkpatch. Hardware qualification remains pending. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
A drive-settings read has a short request and a larger response. Validate both owned-buffer lengths before dispatch, allocate the response capacity, and report its body length without extending the input read. Keep the full response range ownership check before any callback side effect. The 917 codec assertions now include unequal request/response lengths, undersized buffers, limits, and invalid output pointers. Production owned copy tests and all J700 PHY/training/group tests pass under sanitizers. Strict checkpatch and the opaque copy audit are clean. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Use the audited T8140 routing masks for USB3/DP and four-lane DP. The generic sequence changes the miscellaneous lane-swap control and clears routing state that this generation preserves. Update the low protocol fields in order and idle only the PMAs assigned to DisplayPort. Add opt-in callback and PHY completion diagnostics to distinguish firmware waiting from a blocked PHY operation. No calibration values are logged. The routing values are hardware facts from the user-authorized audit; this implementation is independently written. Copy audit clean. Host checks pass: 33 PHY routing/state cases, 112 training bounds, 100 group routing cases, 917 codec assertions, owned-copy and AUX transition tests. Strict checkpatch passes. External-display qualification remains pending. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Keep the newer T602x DP IN clock controls for existing users, but exclude them from the J700 physical DP output. That output uses the original T602x gate sequence and read-clock reset location. The previous generic path wrote the additional source/output gate registers on J700 too. This small condition is derived from audited hardware facts; no private implementation is imported. The production change has no copy-audit matches. Shared generic test-extractor/header boilerplate was reviewed. Validate the actual production mux function for every source on all three outputs, both with and without the J700 condition: 54 select/disconnect scenarios pass under ASan/UBSan. Existing PHY, training and AFK checks pass. Strict checkpatch passes; external hardware qualification remains pending. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Firmware resets the active lane count to zero before setting its link rate. Comparing the following two-lane request against that cached zero rejected a valid activation with EINVAL and prevented link completion. Query the PHY capacity for each request instead. Validate impossible counts before changing state, and propagate validation failures. Cover the zero-to-two reset sequence, unsupported counts and missing PHY. Validation: J700 PHY/training tests, 917 AFK assertions and owned-buffer checks pass under sanitizers; strict checkpatch and copy audit clean. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The V2 request has already passed the physical-capacity check. Restrict the older cached-count warning to the legacy path so a valid zero-to-two transition does not emit an incorrect error. No state transition changes. Validation: J700 host regression tests, strict checkpatch and copy audit. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Keep the separate supply request/override writes and program the link-rate field before the final transmitter output controls. Combining those writes and moving the rate field after output setup did not preserve the audited hardware sequence. The host test now checks the actual production register transaction order, including supply writes. It rejects the previous implementation and passes the corrected sequence for both PMAs and every supported rate/SSC pair. Strict checkpatch and the expanded copy audit pass. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The external firmware asks whether the connection is a virtual display. Return a bounded, zero-initialized physical-device answer instead of unsupported, matching the public m1n1 V2 DPTX protocol. Keep other unknown commands rejected and retain the callback group restrictions. Validation: query size/group checks, J700 training tests, 54 crossbar scenarios, 917 codec assertions and owned-buffer tests; checkpatch and copy audit pass. Hardware qualification remains pending. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Move the firmware DP calibration bundle into the tunable-application phase, before the common supply/clamp sequence. Applying it later from AUX enable preserved the final register values but not the required initialization order. Full DP uses its own common bundle; shared USB/DP keeps the USB lane calibration and then applies the DP bundle. The phase ordering follows the authorized hardware audit. Existing public tunable operations are reused; no private implementation is imported. Actual production-dispatch tests cover full/shared/reversed DP, the legacy path and fixed USB2. Existing PHY, codec and crossbar tests pass. Strict checkpatch passes; only generic test scaffolding matched in the reviewed copy audit. Hardware qualification remains pending. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Missing power-LUT properties on the external controller took the provider failure path and set dcp->crashed before display modes could be published. The existing J700 compatibility payloads were accepted only on the internal controller. Allow those same validated payloads for the explicitly experimental J700 external profile. Keep all request, capacity and property-length checks, and keep malformed properties and other machines/profiles fail-closed. The five existing public payloads match the audited working handoff; no new calibration data is added. Validation: actual provider-callback host tests cover the six known properties, internal compatibility, experimental external compatibility, other profiles/machines, malformed lengths and unknown requests under ASan/UBSan. The old implementation rejects the external regression case. Strict checkpatch and copy audit pass; hardware qualification is pending. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Preserve HBR3 by default and on other outputs. Permit known lower DP rates only for the experimental J700 physical output so training failures can be isolated without changing PHY tables. Exercise the actual callback over all ceilings and scope combinations. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Include validated input/output lengths and channel context in the existing warning. Retain the external fail-closed behavior while identifying the D134 callback observed after link setup. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The external controller reaches video-interface publication, then sends D134 on the async channel with no input and a four-byte output. Its unanswered callback marks the strict external session crashed. Permit the existing zero reply only for that exact record on J700 T8140 DCPEXT. Retain fail-closed behavior for every other unknown external callback and preserve legacy handling. Test the production dispatcher under ASan/UBSan across 15552 tag, size, context and device/profile combinations, including output bounds and unchanged legacy replies. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
R24 reaches external mode export and a visible but frozen image. Firmware uses group 1 command 4 to read training settings during modeset; route it to the bounded native readback helper instead of rejecting it. Test returned cached lane values, no PHY writes and short-reply rejection. Include pending command and present-state information in the existing transaction timeout diagnostic. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The external controller rejects the post-first-present enableGPAlphaDiv property with status 4. Treating that panel workaround as required marks the external session crashed and freezes a visible image. Leave the experimental external controller on its native presentation path while preserving the existing internal-panel property queue. Cover 396 production-queue scope/state/capacity cases and allocation failure under ASan/UBSan. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Run a bounded GTK4 animation on the selected Wayland connector and report draw, frame callback and presentation-feedback counts. The window closes automatically without changing persistent display settings. This allows external presentation to be checked while the operator is away. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Inspect the retained frame history instead of only the immediately preceding frame, whose presentation feedback may still be pending. Report completed timing records separately from presentation timestamps. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Drop temporary protocol capture counters, PHY lock chatter, the global Type-C trace addition and unused link-rate override. Preserve standard tracepoints, failure diagnostics and the validated HBR3 behavior. Register the remaining focused tests and output-frame utility with MAINTAINERS. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Make explicitly enabled external providers participate in component matching before readiness, then validate prepared state after component binding. Reject unpublished or retired DPTX services and preserve stable ownership rather than reusing a published service generation. Retain failed J700 PHY transition state so SAFE retries cleanup, and reject normal training while that state is dirty. Add fault, admission/lifetime and provider-order regressions. A published DPTX service loss remains fail-closed until recovery; these changes do not claim physical hotplug qualification. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Make the host-extracted admission/lifetime checks reproducible alongside the kernel KUnit suite, with repository-relative source selection and an optional source-root override. Generated-by: LLM Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
J700 external DisplayPort previously stopped before mode export, and then froze after its first frame. This opt-in profile now brings the rear Satechi dock up at 1920×1080/60 while preserving the internal panel.
The change supplies the external DCP profile and route, native T8130-layout AUX/PMA/PLL setup, firmware-exported training calibration, and bounded AFKV2/group-aware callbacks. It scopes the measured D134 zero reply to J700 external firmware, handles native training readback during modeset, and keeps the internal-panel enableGPAlphaDiv workaround off DCPEXT. Missing provider data and external bandwidth-resource handling remain explicitly scoped and validated.
Depends on the calibration/DT handoff in aurora-silicon/m1n1#30. No private implementation, firmware binary, calibration blob or key is included. Hardware/protocol facts were audited with owner authorization; the public implementation was written independently and checked against reference-source copying.
Validation:
A separate 180 Hz temporary-layout trial produced 1,849 presentation-feedback frames in 10.591 seconds, then restored the original 60 Hz selection.
Still draft: owner reports washed-out colors and missing monitor identity; runtime selects SDR BT.2020 RGB and the H17P EDID read is disabled. These remain release blockers alongside reviewed external shutdown/restart lifecycle, repeated unplug/replug, orientation/port coverage and suspend/resume qualification. Lifecycle response capture is isolated in draft PR #279; it is not claimed as production-qualified. No display release tag is claimed. The saved release boot entry and recovery artifacts are retained.