Update style configuration and reformat project files

.gitignore

@@ -2,6 +2,7 @@ build/
 
 .idea/
 .vscode/settings.json
+.vim/
 
 test/
 

.rustfmt.toml

@@ -56,8 +56,8 @@ trailing_comma = "Vertical"
 match_block_trailing_comma = false
 blank_lines_upper_bound = 1
 blank_lines_lower_bound = 0
-edition = "2015"
-version = "One"
+edition = "2021"
+style_edition = "2021"
 inline_attribute_width = 0
 format_generated_files = true
 generated_marker_line_search_limit = 5

crates/arcref/src/arcref.rs

@@ -11,7 +11,6 @@ extern crate alloc;
 
 #[cfg(all(not(feature = "std"), feature = "alloc"))]
 use alloc::sync::Arc;
-
 #[cfg(feature = "std")]
 use std::{
     borrow::Borrow,

crates/atomic_unique_refcell/src/lib.rs

@@ -7,7 +7,6 @@ use core::{
     ops::{Deref, DerefMut},
     sync::atomic::{AtomicBool, Ordering},
 };
-
 #[cfg(not(feature = "no_std"))]
 use std::{
     cell::UnsafeCell,

crates/eonix_hal/eonix_hal_macros/src/lib.rs

@@ -2,7 +2,8 @@ extern crate proc_macro;
 
 use proc_macro::TokenStream;
 use quote::quote;
-use syn::{parse, parse_macro_input, spanned::Spanned as _, FnArg, ItemFn};
+use syn::spanned::Spanned as _;
+use syn::{parse, parse_macro_input, FnArg, ItemFn};
 
 /// Define the default trap handler. The function should take exactly one argument
 /// of type `&mut TrapContext`.
@@ -16,7 +17,9 @@ use syn::{parse, parse_macro_input, spanned::Spanned as _, FnArg, ItemFn};
 /// }
 /// ```
 #[proc_macro_attribute]
-pub fn default_trap_handler(attrs: TokenStream, item: TokenStream) -> TokenStream {
+pub fn default_trap_handler(
+    attrs: TokenStream, item: TokenStream,
+) -> TokenStream {
     let item = parse_macro_input!(item as ItemFn);
 
     if !attrs.is_empty() {
@@ -67,15 +70,21 @@ pub fn main(attrs: TokenStream, item: TokenStream) -> TokenStream {
     let item = parse_macro_input!(item as ItemFn);
 
     if !attrs.is_empty() {
-        return parse::Error::new(item.span(), "`main` attribute does not take any arguments")
-            .into_compile_error()
-            .into();
+        return parse::Error::new(
+            item.span(),
+            "`main` attribute does not take any arguments",
+        )
+        .into_compile_error()
+        .into();
     }
 
     if item.sig.inputs.len() != 1 {
-        return parse::Error::new(item.span(), "`main` should have exactly one argument.")
-            .into_compile_error()
-            .into();
+        return parse::Error::new(
+            item.span(),
+            "`main` should have exactly one argument.",
+        )
+        .into_compile_error()
+        .into();
     }
 
     let arg_ident = match item.sig.inputs.first().unwrap() {
@@ -132,9 +141,12 @@ pub fn ap_main(attrs: TokenStream, item: TokenStream) -> TokenStream {
     }
 
     if item.sig.inputs.len() != 1 {
-        return parse::Error::new(item.span(), "`ap_main` should have exactly one argument.")
-            .into_compile_error()
-            .into();
+        return parse::Error::new(
+            item.span(),
+            "`ap_main` should have exactly one argument.",
+        )
+        .into_compile_error()
+        .into();
     }
 
     let arg_ident = match item.sig.inputs.first().unwrap() {

crates/eonix_hal/eonix_hal_traits/src/processor.rs

@@ -1,4 +1,5 @@
-use core::{ops::Deref, pin::Pin};
+use core::ops::Deref;
+use core::pin::Pin;
 
 pub trait Processor {
     fn local() -> impl Deref<Target = Pin<&'static mut Self>>

crates/eonix_hal/src/arch/loongarch64/bootstrap.rs

@@ -1,35 +1,25 @@
-use super::cpu::CPUID;
-use super::cpu::CPU_COUNT;
-use crate::{
-    arch::{
-        cpu::CPU,
-        mm::{ArchPhysAccess, PageAttribute64, GLOBAL_PAGE_TABLE},
-        trap::CSR_KERNEL_TP,
-    },
-    bootstrap::BootStrapData,
-    mm::{
-        flush_tlb_all, ArchMemory, ArchPagingMode, BasicPageAlloc, BasicPageAllocRef,
-        ScopedAllocator,
-    },
-};
-use core::arch::naked_asm;
-use core::{
-    alloc::Allocator,
-    arch::asm,
-    cell::RefCell,
-    sync::atomic::{AtomicBool, AtomicUsize, Ordering},
-};
+use core::alloc::Allocator;
+use core::arch::{asm, naked_asm};
+use core::cell::RefCell;
+use core::sync::atomic::{AtomicBool, AtomicUsize, Ordering};
+
 use eonix_hal_traits::mm::Memory;
-use eonix_mm::{
-    address::{Addr as _, PAddr, PRange, PhysAccess, VAddr, VRange},
-    page_table::{PageAttribute, PagingMode, PTE as _},
-    paging::{Page, PageAccess, PageAlloc, PAGE_SIZE, PFN},
-};
+use eonix_mm::address::{Addr as _, PAddr, PRange, PhysAccess, VAddr, VRange};
+use eonix_mm::page_table::{PageAttribute, PagingMode, PTE as _};
+use eonix_mm::paging::{Page, PageAccess, PageAlloc, PAGE_SIZE, PFN};
 use eonix_percpu::PercpuArea;
-use loongArch64::register::ecfg;
 use loongArch64::register::ecfg::LineBasedInterrupt;
-use loongArch64::register::tcfg;
-use loongArch64::register::{euen, pgdl};
+use loongArch64::register::{ecfg, euen, pgdl, tcfg};
+
+use super::cpu::{CPUID, CPU_COUNT};
+use crate::arch::cpu::CPU;
+use crate::arch::mm::{ArchPhysAccess, PageAttribute64, GLOBAL_PAGE_TABLE};
+use crate::arch::trap::CSR_KERNEL_TP;
+use crate::bootstrap::BootStrapData;
+use crate::mm::{
+    flush_tlb_all, ArchMemory, ArchPagingMode, BasicPageAlloc,
+    BasicPageAllocRef, ScopedAllocator,
+};
 
 #[unsafe(link_section = ".bootstrap.stack")]
 static BOOT_STACK: [u8; 4096 * 16] = [0; 4096 * 16];
@@ -179,8 +169,8 @@ pub unsafe extern "C" fn riscv64_start(hart_id: usize) -> ! {
     }
 
     let start = unsafe {
-        ((&BOOT_STACK_START) as *const &'static [u8; 4096 * 16]).read_volatile() as *const _
-            as usize
+        ((&BOOT_STACK_START) as *const &'static [u8; 4096 * 16]).read_volatile()
+            as *const _ as usize
     };
     let bootstrap_data = BootStrapData {
         early_stack: PRange::new(
@@ -232,7 +222,11 @@ fn setup_kernel_page_table(alloc: impl PageAlloc) {
     flush_tlb_all();
 
     unsafe {
-        core::ptr::write_bytes(KERNEL_BSS_START.addr() as *mut (), 0, BSS_LENGTH as usize);
+        core::ptr::write_bytes(
+            KERNEL_BSS_START.addr() as *mut (),
+            0,
+            BSS_LENGTH as usize,
+        );
     }
 }
 

crates/eonix_hal/src/arch/loongarch64/context.rs

@@ -1,4 +1,5 @@
 use core::arch::naked_asm;
+
 use eonix_hal_traits::context::RawTaskContext;
 
 #[repr(C)]

crates/eonix_hal/src/arch/loongarch64/cpu.rs

@@ -1,9 +1,13 @@
-use super::trap::setup_trap;
+use core::arch::asm;
+use core::pin::Pin;
+use core::ptr::NonNull;
 use core::sync::atomic::AtomicUsize;
-use core::{arch::asm, pin::Pin, ptr::NonNull};
+
 use eonix_preempt::PreemptGuard;
 use eonix_sync_base::LazyLock;
 
+use super::trap::setup_trap;
+
 pub static CPU_COUNT: AtomicUsize = AtomicUsize::new(0);
 
 #[eonix_percpu::define_percpu]

crates/eonix_hal/src/arch/loongarch64/fdt.rs

@@ -1,9 +1,11 @@
-use super::mm::ArchPhysAccess;
 use core::sync::atomic::{AtomicPtr, Ordering};
+
 use eonix_mm::address::{Addr, PAddr, PRange, PhysAccess};
 use eonix_sync_base::LazyLock;
 use fdt::Fdt;
 
+use super::mm::ArchPhysAccess;
+
 const FDT_PADDR: PAddr = PAddr::from_val(0x100000);
 
 pub static FDT: LazyLock<Fdt<'static>> = LazyLock::new(|| unsafe {

crates/eonix_hal/src/arch/loongarch64/fence.rs

@@ -1,7 +1,5 @@
-use core::{
-    arch::asm,
-    sync::atomic::{compiler_fence, Ordering},
-};
+use core::arch::asm;
+use core::sync::atomic::{compiler_fence, Ordering};
 
 #[doc(hidden)]
 /// Issues a full memory barrier.

crates/eonix_hal/src/arch/loongarch64/fpu.rs

@@ -1,4 +1,5 @@
 use core::arch::asm;
+
 use eonix_hal_traits::fpu::RawFpuState;
 
 #[repr(C)]

crates/eonix_hal/src/arch/loongarch64/interrupt/mod.rs

@@ -15,10 +15,11 @@
 //! tree advertises for the interrupt controller (`interrupts = <3>`), and
 //! every vector to CPU 0.
 
-use super::mm::ArchPhysAccess;
 use eonix_mm::address::{PAddr, PhysAccess};
 use loongArch64::iocsr;
 
+use super::mm::ArchPhysAccess;
+
 /// Base address of the PCH-PIC (normal MMIO).
 const PCH_PIC_BASE: usize = 0x1000_0000;
 
@@ -76,14 +77,16 @@ fn pch_write8(offset: usize, value: u8) {
 }
 
 fn eiointc_enable_vector(vector: usize) {
-    let offset = EIOINTC_ENABLE + (vector / EIOINTC_GROUP_SIZE) * size_of::<u32>();
+    let offset =
+        EIOINTC_ENABLE + (vector / EIOINTC_GROUP_SIZE) * size_of::<u32>();
     let bit = 1u32 << (vector % EIOINTC_GROUP_SIZE);
 
     iocsr::iocsr_write_w(offset, iocsr::iocsr_read_w(offset) | bit);
 }
 
 fn eiointc_clear_vector(vector: usize) {
-    let offset = EIOINTC_COREISR + (vector / EIOINTC_GROUP_SIZE) * size_of::<u32>();
+    let offset =
+        EIOINTC_COREISR + (vector / EIOINTC_GROUP_SIZE) * size_of::<u32>();
     let bit = 1u32 << (vector % EIOINTC_GROUP_SIZE);
 
     // Writing one acknowledges (clears) the pending bit.
@@ -105,7 +108,10 @@ pub fn init() {
     // Route all vectors to CPU 0.  COREMAP stores four bytes (one vector
     // each) per 32-bit register; a byte holds a bitmask of target CPUs.
     for word in 0..(EIOINTC_VECTORS / 4) {
-        iocsr::iocsr_write_w(EIOINTC_COREMAP + word * size_of::<u32>(), 0x0101_0101);
+        iocsr::iocsr_write_w(
+            EIOINTC_COREMAP + word * size_of::<u32>(),
+            0x0101_0101,
+        );
     }
 }
 

crates/eonix_hal/src/arch/loongarch64/mm.rs

@@ -1,30 +1,29 @@
-use crate::traits::mm::Memory;
-use core::{
-    arch::asm,
-    marker::PhantomData,
-    ptr::NonNull,
-    sync::atomic::{compiler_fence, Ordering},
-};
-use eonix_mm::{
-    address::{Addr as _, AddrOps, PAddr, PRange, PhysAccess, VAddr},
-    page_table::{
-        PageAttribute, PageTable, PageTableLevel, PagingMode, RawAttribute, RawPageTable,
-        TableAttribute, PTE,
-    },
-    paging::{NoAlloc, Page, PageBlock, PAGE_SIZE, PFN},
+use core::arch::asm;
+use core::marker::PhantomData;
+use core::ptr::NonNull;
+use core::sync::atomic::{compiler_fence, Ordering};
+
+use eonix_mm::address::{Addr as _, AddrOps, PAddr, PRange, PhysAccess, VAddr};
+use eonix_mm::page_table::{
+    PageAttribute, PageTable, PageTableLevel, PagingMode, RawAttribute,
+    RawPageTable, TableAttribute, PTE,
 };
+use eonix_mm::paging::{NoAlloc, Page, PageBlock, PAGE_SIZE, PFN};
 use eonix_sync_base::LazyLock;
 use loongArch64::register::pgdl;
 
+use crate::traits::mm::Memory;
+
 pub const KIMAGE_OFFSET: usize = 0xffff_ffff_0000_0000;
 pub const ROOT_PAGE_TABLE_PFN: usize = 0x8000_1000 >> 12;
 pub const PAGE_TABLE_BASE: PFN = PFN::from_val(ROOT_PAGE_TABLE_PFN);
-pub static GLOBAL_PAGE_TABLE: LazyLock<PageTable<ArchPagingMode, NoAlloc, ArchPhysAccess>> =
-    LazyLock::new(|| unsafe {
-        Page::with_raw(PAGE_TABLE_BASE, |root_table_page| {
-            PageTable::with_root_table(root_table_page.clone())
-        })
-    });
+pub static GLOBAL_PAGE_TABLE: LazyLock<
+    PageTable<ArchPagingMode, NoAlloc, ArchPhysAccess>,
+> = LazyLock::new(|| unsafe {
+    Page::with_raw(PAGE_TABLE_BASE, |root_table_page| {
+        PageTable::with_root_table(root_table_page.clone())
+    })
+});
 
 pub const PA_VP: u64 = ((1 << 0) | (1 << 7));
 pub const PA_D: u64 = 1 << 1;
@@ -243,8 +242,12 @@ impl PhysAccess for ArchPhysAccess {
 
 impl Memory for ArchMemory {
     fn present_ram() -> impl Iterator<Item = PRange> {
-        let range1 = core::iter::once(PRange::from(PAddr::from_val(0)).grow(0x1000_0000));
-        let range2 = core::iter::once(PRange::from(PAddr::from_val(0x8000_0000)).grow(0x3000_0000));
+        let range1 = core::iter::once(
+            PRange::from(PAddr::from_val(0)).grow(0x1000_0000),
+        );
+        let range2 = core::iter::once(
+            PRange::from(PAddr::from_val(0x8000_0000)).grow(0x3000_0000),
+        );
 
         range2.chain(range1)
     }
@@ -261,7 +264,8 @@ impl Memory for ArchMemory {
 
         Self::present_ram()
             .filter(move |range| {
-                range.end() <= kernel_start || range.end() > paddr_after_kimage_aligned
+                range.end() <= kernel_start
+                    || range.end() > paddr_after_kimage_aligned
             })
             .map(move |range| {
                 if range.end() > paddr_after_kimage_aligned

crates/eonix_hal/src/arch/loongarch64/trap/mod.rs

@@ -1,21 +1,20 @@
 mod trap_context;
 
-use super::context::TaskContext;
 use core::arch::{asm, global_asm, naked_asm};
 use core::cell::UnsafeCell;
 use core::mem::{offset_of, size_of};
 use core::num::NonZero;
 use core::ptr::NonNull;
-use eonix_hal_traits::{
-    context::RawTaskContext,
-    trap::{IrqState as IrqStateTrait, TrapReturn},
-};
+
+use eonix_hal_traits::context::RawTaskContext;
+use eonix_hal_traits::trap::{IrqState as IrqStateTrait, TrapReturn};
 use loongArch64::register::crmd::{self, Crmd};
 use loongArch64::register::ecfg;
 use loongArch64::register::eentry::{self, Eentry};
-
 pub use trap_context::*;
 
+use super::context::TaskContext;
+
 pub const CSR_KERNEL_TP: usize = 0x30;
 const CSR_CAPTURED_TRAP_CONTEXT_ADDR: usize = 0x31;
 const CSR_CAPTURER_TASK_CONTEXT_ADDR: usize = 0x32;