ECE284 2D Systolic Array Project

Key Accomplishments

• Implemented and verified a 2D systolic array accellerator chip, supporting runtime-configurable weight-stationary and output-stationary modes, and single 4-bit activations or two 2-bit activations.
• Built an automated multi-layer verification framework in Python and completed FPGA synthesis, collecting frequency, power, and TOPS/TOPS-per-Watt numbers for both the baseline and reconfigurable designs.

Extras

1. Multi-Layer Verification Framework using Python Random Generation
2. MaxPool2D Implementation in SFU
3. SFU Floating Point Re-Conversion

File Structure

├── src
│   ├── tensors
│   │   │   └── *.txt         # Activation, psum, and weight values for testbench
│   ├── visualize
│   │   ├── output_k3.txt     # Test output for 3x3 kernel (k = 3, n = 1)
│   │   ├── output_k5.txt     # Test output for 5x5 kernel (k = 5, n = 1)
│   │   └── visualize.ipynb   # Plot performance against feature size
│   ├── verilog
│   │   ├── core.v            # Contains SRAM, corelet
│   │   ├── corelet.v         # Contains MAC array, I/O FIFOs, SFU
│   │   ├── fifo.v            # Contains multiple FIFO modules
│   │   ├── iofifo.v          # I/O FIFO
│   │   ├── mac.v             # Contains MAC array, row, and cell modules
│   │   ├── project_tb.v      # Parameterized testbench w/ comprehensive testing
│   │   ├── sfu.v             # SFU w/ ReLU, MaxPool, fp16 conversion
│   │   └── sram_32b_w2048.v  # SRAMs
│   ├── filelist              # Files to include for synthesis
│   └── generate_tests.ipynb  # Parameterized test generator
├── README.md
└── report.pdf