SystemC - #662
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desmonddak wants to merge 96 commits into
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…al/instance naming routine names
Clarify comment Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
This aligns central_naming with the simplified naming approach already adopted by all downstream branches (module_services, netlist, source_debug, systemc_trace, fst-writer). Changes: - Remove Namer._instanceNames cache field - Remove Namer.instanceNameOf(Module) method - Update synthesizers to use Namer.allocateName(String) directly - Remove destination tracking from _BusSubsetForStructSlice Benefit: Eliminates duplication across 5+ branches, making each branch truly orthogonal and mergeable without conflicts. Trade-off: Instance names no longer cached across synthesis passes, but all downstreams already use this simpler approach.
# Conflicts: # tool/gh_codespaces/install_dart.sh
Moved from Options to Configuration nomenclature. Dependency on rohd_hierarchy so we can use Occurrence classes Leverage Namer and eliminate residual naming functionality. Remove warnings and move to just throw on error.
…ells, and using enum for port dirs
Exact cumulative tree from original branch 7412bd260ddd235b6005d54ae7dadba372fad0b3 in the netlist-first merge order.
Exact cumulative tree from original branch a6e3a10b7d2693691fe99cac541614f028a9f8fb in the netlist-first merge order.
added 3 commits
August 24, 2026 14:35
Exact cumulative tree from original branch 66a3353fc069018312982b94666735add2f81eb6 in the netlist-first merge order.
Exact cumulative tree from original branch 40652d1b2381cb39dff8c754f1ef1a43309615f9 in the netlist-first merge order.
Exact cumulative tree from original branch f61b48ae8deb1d65500df6174faeb47bd5adfceb in the netlist-first merge order.
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Description & Motivation
We should have a SystemC translation of our ROHD modules to simulate in a SystemC environment.
Related Issue(s)
None.
Testing
Leverage iverilog tests to drive SystemC testing, except for somethings like lack of 'X' propagation.
Backwards-compatibility
No.
Documentation
Very basic documentation added to parallel SystemVerilog.