All pull requests

Pull requests

• Bump vtr-verilog-to-routing from 0b91233 to 4b4a3a8

  dependenciessubmodules
  #2856·dependabot[bot] opened Nov 3, 2026Bot·

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• Bump yosys from e0bf46e to 8e6c9dc

  dependenciessubmodules
  #2855·dependabot[bot] opened Nov 3, 2026Bot·

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• Bump pylint from 2.7.4 to 4.0.9

  dependenciespython
  #2854·dependabot[bot] opened Nov 2, 2026Bot·

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• Run Python scripts as the shell of a task, and call shell commands as methods

  documentationflow-scriptsopenfpga-toolstests
  #2847·ganeshgore opened Oct 29, 2026Collaborator·8/8·

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• Check the commands after the stages against the flow, and read stage results from files

  documentationopenfpga-toolsVPR
  #2846·ganeshgore opened Oct 28, 2026Collaborator·7/8·

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• Add commands to read the inputs and run pack, place and route one stage at a time

  documentationflow-scriptsopenfpga-tools
  #2843·ganeshgore opened Oct 27, 2026Collaborator·6/8·

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• Add typed application options, generated from VPR, with set_app_option and report_app_option

  documentationflow-scriptsopenfpga-tools
  #2840·ganeshgore opened Oct 27, 2026Collaborator·5/8·

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• Add OpenFpgaSession to track the inputs and stages of a stage-by-stage flow

  openfpga-tools
  #2838·ganeshgore opened Oct 26, 2026Collaborator·4/8·

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• Fix crash when running vpr a second time in one process

  openfpga-tools
  #2835·ganeshgore opened Oct 26, 2026Collaborator·3/8·

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• Add error mapping and per-command log capture to the Python binding

  openfpga-tools
  #2833·ganeshgore opened Oct 26, 2026Collaborator·2/8·

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• Add Python binding for the OpenFPGA shell (SWIG) with smoke tests

  buildgithublang-makeopenfpga-tools
  #2832·ganeshgore opened Oct 26, 2026Collaborator·1/8·

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• Bump black from 26.3.1 to 26.10.1

  dependenciespython
  #2830·dependabot[bot] opened Oct 25, 2026Bot·

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• [WIP] add WASI build

  github
  #2519·tangxifan opened May 13, 2026Collaborator·

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• [WIP] VPR command intergration

  builddocumentationflow-scriptslang-makeopenfpga-toolsVPR
  #2473·ganeshgore opened Apr 24, 2026Collaborator·

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• [WIP] Remapping Bitstream

  architecture-descriptiondocumentationflow-scriptsopenfpga-bitstreamopenfpga-toolstests
  #2414·ganeshgore opened Mar 6, 2026Collaborator·

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  2

  

• [fabric_bitstream] Adding custom bitstream remap

  openfpga-bitstreamopenfpga-tools
  #2022·amin1377 opened Jun 4, 2025Collaborator·

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  4

• Use hierarchical block names

  openfpga-toolsVPRwontfix
  #1976·amin1377 opened Apr 7, 2025Collaborator·

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• Add command to generate repack design constraints

  openfpga-tools
  #1889·fkosar-ql opened Nov 6, 2024Collaborator·

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  8

  

• Make sure net is valid before setting it as wire LUT output

  openfpga-tools
  #1719·chungshien opened Jun 19, 2024Collaborator·

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  7

• Preserve escaped names

  openfpga-toolsopenfpga-verilog
  #1589·alaindargelas opened Mar 4, 2024·

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  3

• Update FindTBB.cmake

  #1238·yppah56 opened Jun 27, 2023·

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• Update FindTBB.cmake

  #1161·zaidtahirbutt opened May 10, 2023·

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  2

• Relative paths in run_modelsim.py and other changes to make Modelsim work on non-Utah machines

  architecture-descriptionflow-scripts
  #247·nachiket opened Feb 20, 2021Contributor·3 of 16 tasks·

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  9