There was an error while loading. Please reload this page.
An open-source Ternary Content Addressable Memory (TCAM) compiler.
Python 37 15
Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
SystemVerilog 34 10
Project ideas list for Google Summer of Code.
18 2
A basic System on a Chip (SoC) based on the Buraq core for the Internet of Things (IoT).
Verilog 6 2
TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
Scala 25 11
This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)
Scala 11 6
Post Quantum Adaptive Encryption Secure Communication System
NucleusRV (RV32-IMAFC) - A 32-bit 5 staged pipelined risc-v core.
Open-source RISC-V Vector accelerated sparse linear algebra library.
Clean slate application using NDN with Dilithium to enhance security in future internet technology
Hallucination reduction framework for LLMs using RAG, multi-discriminator RL, and automated data pipelines.
Project Ideas for European Summers of code
A RISC-V Simulator
