Digital hardware · Semiconductor design · Engineering education
Honors Electrical Engineering at the University of Minnesota, College of Science and Engineering.
I build digital hardware and the tools and learning material that help people understand it. My work spans processor architecture, matrix accelerators, FPGA implementation, open-source ASIC flows, and scientific computing. I lead Stone Arch Silicon at UMN and contribute to the ASIC Network.
LinkedIn · Portfolio source and interactive demos
| Project | What to look at | Evidence in the repository |
|---|---|---|
| 2×2 systolic accelerator | Output-stationary processing elements, operand scheduling, and an OpenLane/SKY130 implementation | Architecture, waveforms, physical-design documentation, and a committed GDSII layout |
| RV64I pipelined CPU | Five pipeline stages, hazard handling, forwarding, and memory interfaces | SystemVerilog source, architecture notes, and a bubble-sort testbench |
| FPGA sequential multiplier | Parameterized arithmetic and the path from RTL to a Basys 3 implementation | RTL, testbench, board constraints, and timing documentation |
| ASIC 101 | Teaching an end-to-end hardware flow through one 8-bit ALU | 25 lessons covering RTL, verification, FPGA implementation, physical design, and engineering handoff |
For a quick technical review, start with the systolic accelerator’s architecture and layout, then the CPU’s pipeline and testbench.
Stone Arch Silicon — our UMN semiconductor-design community. The club site, ASIC 101 course, documentation book, and shared documentation theme connect projects with a path for new contributors.
ASIC Network — collaborative infrastructure for people learning and building chips: a community website, analog tutorials, digital tutorials, and benchmarked-silicon planning.
These are team projects. Repository histories credit the people who build them.
| Area | Repositories |
|---|---|
| Arithmetic experiments | Parallel matrix multiplier · Earlier systolic implementation — archived · Club systolic project |
| Numerical formats | Posit8 Lab — project setup · 8-bit posit codec documentation · Interactive posit lab in my portfolio |
| Learning and exploration | CUDA exercises · Verilog practice |
| Embedded systems | EE2361 final project · SkyLab collaboration fork |
| Scientific computing | GW-NN experiments · Neutrino energy-estimation fork · Aframe research fork |
| Community software | UMN Sri Lankan Students' Association site |
The featured projects above are the best entry points; this directory shows the broader experiments and collaborations behind them.
SystemVerilog / Verilog · Vivado · OpenLane / SKY130 · Python · CUDA · C / C++ · Git · mdBook · HTML / CSS / JavaScript
I'm interested in the full chain: understanding an architecture, implementing it, testing it, reading the reports, and making the result understandable to the next engineer.