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IIT Bhubaneswar
- Bhubaneswar, Odisha, India
- in/spandan-mondal-113338288
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UART-controller-ASIC-flow
UART-controller-ASIC-flow PublicComplete RTL-to-GDSII implementation of a UART Controller using SystemVerilog, OpenLane 2, and the Sky130 open-source ASIC flow.
SystemVerilog 1
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ESP32-OLED-Music-Display
ESP32-OLED-Music-Display PublicAn ESP32-based embedded music display system that shows currently playing YouTube Music track information and lyrics on an OLED display.
Python 1
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FPGA_based__MLP_accelerator
FPGA_based__MLP_accelerator PublicFPGA-based MLP inference accelerator in SystemVerilog — classifies MNIST handwritten digits using a 4-layer neural network with AXI4-Lite interface, fixed-point arithmetic, and sigmoid/ReLU activat…
SystemVerilog 1
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AutoCAD-Electrical-Motor-Control-Panel
AutoCAD-Electrical-Motor-Control-Panel PublicComplete electrical control panel design created using AutoCAD Electrical with schematic and panel layout drawings.
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