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Summary
Reduce fused-vector allocation by generating whole-run float32, float64 and mixed-precision loops. Prefer eager vector ufuncs for direct single-operation expressions, reduce small-expression eager setup, and add allocation and contraction benchmarks.
Add an experimental, explicitly closed
NJ.parallel(workers)context for selected contiguous float32/64 unary and binary ufuncs, expressions and deterministic full-array sum. Confined memory, unsafe overlap, unsupported layouts and small inputs use existing caller-thread paths. Fixed sum chunks and merge order are independent of worker count. The parallel execution guide documents lifecycle, scope closure, nesting and numerical limits.Validation
build, fused-provider tests and the fused-expression example passed before the final nested-context and interruption fixes; targeted parallel context, stress and expression tests passed afterward.ac454b5.Open evidence and readiness
E04 prepares the reference campaign; the user's Ryzen 9 5950X run has not been performed on this revision. Worker scaling, crossover thresholds, dot/vecdot reference measurements and the earlier 0.5.0 fusion/allocating/AUTO performance gates remain open. No target has been silently waived. See
docs/benchmarks/M4-reference-protocol.md,docs/benchmarks/M4-performance-status.mdanddocs/milestones/M4-0.6-release-checklist.md.Keep this PR draft until the outstanding reference evidence is reviewed. No tag or publication is implied.