arithmetic-circuits

A language for intent-centric and declarative decentralised applications

🕸️ Graphs, finite fields and discrete dynamical systems in Kotlin

A framework to execute and verify algorithms using Groth16 zkSNARKs.

ZPiE: Zero-knowledge Proofs in Embedded systems

Sparse Circuits on the GPU (ICLR2025)

Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.

Rank-1 Constraint System (R1CS) to Quadratic Arithmetic Program (QAP) transformation using polynomial roots and witness verification.

Plonk grand product copy-constraint permutation argument tracking wire routing equality

Rank-1 Constraint System (R1CS) to Quadratic Arithmetic Program (QAP) transformation using polynomial roots and witness verification.

Plonk grand product copy-constraint permutation argument tracking wire routing equality

Experiments with circuit compilation and zk-snarks

Circuit building utilities

Circuits, Proofs, and Algebra: research papers and reproducible code on complexity lower bounds, motivated by P vs NP and VP vs VNP.

Rust implementation of some Arithmetization-Oriented cryptographic primitives in the Plonk framework

A collection of synthesizable hardware modules and digital design patterns implemented in SystemVerilog. Features optimized RTL for arithmetic units (BCLA, Booth's algorithm) and memory structures (Sync FIFO) with verification suites.

Fault injection environment (finjenv) of permanent hardware faults for various arithmetic circuits based on QuestaSIM logic simulator

Sublinear-space zero-knowledge proof system with production REST API. TinyZKP is a high-performance ZKP prover/verifier that uses only O(√T) memory for proofs over traces of length T, rather than the typical O(T) that most systems require.

CompiledKnowledge is a Python package for compiling and querying discrete probabilistic graphical models.

CPEN 311: Digital Systems Design

Designed and simulated ultra low-voltage, low-power CMOS 5:2 compressors in Cadence Virtuoso, based on Figure 13 from the referenced IEEE paper. Focused on optimizing power, delay, and area for efficient high-speed arithmetic circuits used in VLSI and DSP applications.