Skip to content

Actions: vortexgpgpu/vortex

Actions

All workflows

Actions

Loading...
Loading

Showing runs from all workflows
1,258 workflow runs
1,258 workflow runs

Filter by Workflow

⌥ + click/return to exclude

Filter by Event

⌥ + click/return to exclude

Filter by Status

⌥ + click/return to exclude

Filter by Branch

⌥ + click/return to exclude

Filter by Actor

⌥ + click/return to exclude
simx: stop reseeding the host C RNG in the scheduler constructor CI #1903: Commit 4db71f3 pushed by tinebp
In progress master
master
In progress
Vulkan rt (#424) CI #1902: Commit 6f372b0 pushed by tinebp
22m 47s master
master
22m 47s
Vulkan rt CI #1901: Pull request #424 opened by tinebp
52m 55s vulkan-rt
vulkan-rt
52m 55s
vxbin: read kernel entries from readelf columns, not a decimal-size p… CI #1900: Commit 833a108 pushed by tinebp
4m 15s vulkan-rt
vulkan-rt
4m 15s
ci: add a wide-issue suite at the default execution-block count CI #1899: Commit 61ddbac pushed by tinebp
58m 28s master
master
58m 28s
FPGA Gate FPGA Gate #37: Manually run by tinebp
5h 24m 33s master
master
5h 24m 33s
ASIC Gate ASIC Gate #32: Scheduled
20m 29s master
master
20m 29s
simx: model the issue lock, per-slot dispatch queues and port-0 flush… CI #1898: Commit 5eec172 pushed by tinebp
5h 18m 52s master
master
5h 18m 52s
simx: model the issue lock, per-slot dispatch queues and port-0 flush register as the RTL builds them CI #1897: Pull request #423 synchronize by tinebp
7m 9s simx-parity-issue-lock
simx-parity-issue-lock
7m 9s
Merge branch 'master' into simx-parity-issue-lock CI #1896: Commit 529458f pushed by tinebp
7m 19s simx-parity-issue-lock
simx-parity-issue-lock
7m 19s
afu: route the command processor through the bank adapter on multi-po… CI #1895: Commit f63adcf pushed by tinebp
7m 43s master
master
7m 43s
simx: model the issue lock, per-slot dispatch queues and port-0 flush register as the RTL builds them CI #1894: Pull request #423 synchronize by tinebp
3m 47s simx-parity-issue-lock
simx-parity-issue-lock
3m 47s
ci: run the synthesis gates only on nights that follow a synthesis-in… CI #1893: Commit aa23cad pushed by tinebp
20s simx-parity-issue-lock
simx-parity-issue-lock
20s
simx: model the issue lock, per-slot dispatch queues and port-0 flush register as the RTL builds them CI #1892: Pull request #423 opened by tinebp
5m 25s simx-parity-issue-lock
simx-parity-issue-lock
5m 25s
simx: model the issue lock, per-slot dispatch queues and port-0 flush… CI #1891: Commit f1bb2f6 pushed by tinebp
5m 24s simx-parity-issue-lock
simx-parity-issue-lock
5m 24s
ASIC Gate ASIC Gate #31: Scheduled
35s master
master
35s
FPGA Gate FPGA Gate #36: Scheduled
51s master
master
51s
ASIC Gate ASIC Gate #30: Scheduled
31s master
master
31s
FPGA Gate FPGA Gate #35: Scheduled
17s master
master
17s
ASIC Gate ASIC Gate #29: Scheduled
21m 42s master
master
21m 42s
FPGA Gate FPGA Gate #34: Scheduled
5h 18m 36s master
master
5h 18m 36s
afu: route the command processor through the bank adapter on multi-port shells CI #1890: Pull request #422 opened by tinebp
10h 3m 25s fix/afu-multibank-cp
fix/afu-multibank-cp
10h 3m 25s
afu: route the command processor through the bank adapter on multi-po… CI #1889: Commit afb88b6 pushed by tinebp
10h 55m 30s fix/afu-multibank-cp
fix/afu-multibank-cp
10h 55m 30s
tfr_isfpga2: GPU-generation sweep with FEDP2K (N=8) and fanout CI #1888: Commit c0f11b4 pushed by NikhilRout
47s feature_mx
feature_mx
47s
Merge branch 'master' of https://github.com/vortexgpgpu/vortex CI #1887: Commit b8c5a24 pushed by tinebp
7h 25m 0s master
master
7h 25m 0s