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Achievement: Pull Shark

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Achievement: Pull Shark

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@asicwru

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AxC1271/README.md

Andrew Chen

Computer Engineer | Hardware Design | RISC-V Architecture

Design Lead @ ASICWRU — CWRU CHIPS ASIC Design

View my taped-out ASICs: CWRU CPU · Tiny Pong

About Me

Interested in needle-felting, poetry, music, and baking. Outside of work: skateboarding, chess, handstand push-ups, reading, and sleeping.

Tech Stack

Hardware Languages & Design

RISC-V SystemVerilog Verilog VHDL

EDA & Verification Tools

Vivado Yosys OpenSTA SymbiYosys KiCad Icarus Verilog

Programming Languages

C Python Bash Assembly

Platforms & Microcontrollers

ARM Intel Xilinx Raspberry Pi STM32 FPGA

Development Tools & OS

Linux Git Docker CMake LaTeX

Project Highlights
RISC-V SoC v3 (In Progress) 2-way superscalar in-order processor with Gshare branch predictor. Explores instruction-level parallelism, hazard detection, and branch prediction accuracy across bimodal and global-history designs. SystemVerilog. View Repo →
RISC-V SoC v2 5-stage pipelined RV32I processor with split L1 caches (direct-mapped I-cache, 2-way D-cache). Complete RTL implementation and STA analysis (58.8 MHz post-synth, 85 MHz FPGA). SystemVerilog. View Repo →
CWRU CPU — Hacker Fab Led underclassmen design team to implement single-cycle RISC-V processor and tape out via Tiny Tapeout (June 2026). Verilog, RISC-V. View Repo → · GDS Viewer →
Tiny Pong — SkyWater 130nm Pong VGA controller taped out on SkyWater 130nm via Tiny Tapeout. First custom silicon project publicly available. Verilog. View Repo → · GDS Viewer →
STM32 Dev Board Custom STM32F103 development board designed in KiCad 7.0, fabricated at JLCPCB. VHDL UART receiver validated on Basys3 FPGA. View Repo →
ASICWRU Handbook Comprehensive open guide to digital systems design, from logic gates to silicon. Built for CWRU students and hardware design enthusiasts. Python, Verilog. View Repo →

Pinned Loading

  1. RISCV-v3 RISCV-v3 Public

    This repository features a 2-way superscalar in-order processor supporting various types of branch predictor schemes. Static timing analysis, simulations, and formal verification techniques will be…

    SystemVerilog 1

  2. RISCV-v2 RISCV-v2 Public

    This repository contains a 5-stage in-order pipelined processor that builds on a previous RISC-V CPU GitHub repository in SystemVerilog, but it adds a split L1 cache hierarchy for both instructions…

    SystemVerilog 1

  3. RISCV-v1 RISCV-v1 Public

    This is a RTL approach to implementing a single-cycle RISC-V processor using VHDL and the Basys3 FPGA board. Fully synthesizable with instructions to run a simple Fibonacci sequence.

    VHDL 1

  4. mini-NPU mini-NPU Public

    This repository explores hardware acceleration through the RTL design of a neural processing unit (NPU). The core implements INT8 multiply-accumulate operations using a systolic-array-based archite…

    SystemVerilog 1

  5. TinyPong TinyPong Public

    This is a TinyTapeout submission (TT-Sky25b) of a simple single-player Pong game written in Verilog as an addition to my original VGA Pong project. The final project is then fabbed onto a physical …

    Verilog 1

  6. ASICWRU-Handbook ASICWRU-Handbook Public

    A comprehensive, openly written guide to digital systems design — from logic gates to silicon. Built for CWRU students and anyone curious about hardware design, with the goal of making ASIC educati…

    SystemVerilog 6