Student-led silicon design and chip tapeout team at Case Western Reserve University.
We are an undergraduate engineering organization dedicated to taking digital, analog, and mixed-signal designs from architecture and RTL down to physical layout, verification, and tapeout.
We bridge the gap between classroom computer systems theory and physical silicon. Our members design custom digital logic, build custom accelerators, run synthesis and static timing analysis (STA), and implement full physical layout using both open-source (OpenROAD, Yosys, OpenSTA) and commercial EDA toolchains.
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Audio FIR Filter Tapeout (Active, Fall 2026 - Ongoing)
A dedicated digital signal processing chip implementing a configurable finite impulse response (FIR) filter for real-time audio equalization and noise filtering. The design focuses on hardware-efficient multiply-accumulate (MAC) datapaths, I2S/SPI peripheral interfaces, and low-power ASIC implementation. -
Single-Cycle RV32I Processor (Finished, Spring 2026)
Our foundational microarchitecture project: a functional 32-bit RISC-V core implementing the base unprivileged integer instruction set (RV32I). Built in SystemVerilog/Verilog with a custom test harness, automated assembly verification, and full synthesis down to standard cells.
- HDLs/Layout: SystemVerilog, Verilog, Magic VLSI
- Verification & Sim: Verilator, Icarus Verilog, cocotb, GTKWave, ngspice
- ASIC Implementation: OpenROAD, Yosys, OpenSTA, SkyWater 130nm / Tiny Tapeout flows
- Target Hardware: Custom ASICs, Xilinx/Digilent FPGA prototyping
We welcome CWRU students interested in digital design, microarchitecture, physical design, and embedded verification. No prior tapeout experience is required; we run onboarding tracks covering hardware description languages, digital logic verification, and physical design basics.
- Campus Meetings: Weekly lab working sessions (Check our campus groups page or Discord for room updates).
- Contact: Reach out via our club officers or open an issue/discussion right here on GitHub.
