Welcome to the museum! Each "exhibit" is a fully characterized digital cell: from basic logic gates to sequential elements, designed using open-source EDA tools. This project documents my journey learning IC design from the ground up.
This is a personal collection of custom VLSI standard cells that I made using Xschem (schematic), Magic (layout), ngspice (simulation), and with netgen (complete verification). As a computer
engineering student at Case, I grew interested in CMOS IC design but felt disheartened because industry tools like Cadence Virtuoso are extremely expensive and not easily accessible to most students. Luckily, the tools I used for this project are all open source and can be easily installed using apt-get commands on Ubuntu Linux. Check the download_instructions.txt file in the repo to see how to download these open source tools!
- Inverter - The Hello World
- NAND Gate - The Universal Gate
- NOR Gate - Dual of NAND, efficient pull-up network
- AND Gate - NAND followed by inversion
- OR Gate - NOR followed by inversion
- XOR Gate - Transmission gate implementation for efficiency
- 2:1 Multiplexer - Input selector
- Full Adder - 1-bit addition with carry propagation
- D-Latch - Level-sensitive storage element
- D Flip-Flop - Edge-triggered master-slave configuration
- D Flip-Flop with Enable - Conditional loading register
| Tool | Purpose |
|---|---|
| Xschem | Schematic capture and SPICE netlist generation |
| Magic VLSI | Full-custom layout editor with integrated DRC |
| ngspice | Circuit simulation and timing analysis |
| Netgen | Layout vs. Schematic (LVS) verification |
| PDK | Sky130 (SkyWater 130nm open-source PDK) |
Clone the museum:
git clone https://github.com/yourusername/cell-museum.git
cd cell-museumBuilt with curiosity and caffeine ☕ at Case Western Reserve University