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drm/asahi: reserve the M5 UAPI feature bits, command types and bind flag - #273
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The Aurora Mesa that omacom/mesa is syncing (omacom/mesa#19) defines feature bits 17 to 24, 26 and 28, command types 5 to 7 and DRM_ASAHI_BIND_SPARSE_TILE for the M5 (G17G/G17S) runtime. This header defines none of them. Mesa only uses each one after the kernel reports its feature bit, and this kernel never does, so nothing runs today. But if one of those numbers were later given to something else, Mesa would take an M5 path this kernel does not have. Reserve them under Mesa's names and values. Each entry says it belongs to the M5 runtime, and the comment before the feature bits notes that bits 25 and 27 are reserved for it too. This kernel already rejects the command types and the bind flag with EINVAL, and it reports none of the feature bits. Signed-off-by: DjDeveloperr <hey@djdev.me>
DjDeveloperr
requested review from
chriskearney,
maralcbr and
scottjones
as code owners
October 29, 2026 03:56
This was referenced Oct 29, 2026
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Requested by maralcbr in his review of omacom/mesa#19.
The Aurora Mesa that #19 syncs defines these values for the M5 (G17G/G17S) runtime, and this header defines none of them:
SET_RENDER_RESOURCES,SET_COMPUTE_RESOURCES,SET_RENDER_RESOURCES_V2);DRM_ASAHI_BIND_SPARSE_TILE.Mesa only uses each one after the kernel reports its feature bit, and this kernel never does, so nothing runs today. But if one of those numbers were later given to something else, Mesa would take an M5 path this kernel doesn't have.
This reserves them under Mesa's names and values:
_ => EINVAL) and the bind flag (explicit flag mask), and it reports none of the feature bits.Testing:
include/drm-uapi/asahi_drm.hexactly.scripts/kernel-doc -Wallreports nothing new.DRM_ASAHI=m, with G15 and M3_T8122).