🎓 Path to a free self-taught education in Computer Science!
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Updated
Jun 20, 2022
🎓 Path to a free self-taught education in Computer Science!
Scan insertion and design of a LBIST wrapper for a RISC-V core for stuck-at fault model
Path-Oriented Decision Making (PODEM) algorithm for Automatic Test Pattern Generation (ATPG).
A scientific framework for researching automatic test pattern generation (ATPG)
Simple EDA tool for fault reduction and testing for combinational circuits
Scientific tool to insert Reconfigurable Scan Networks (RSN) into synthesized circuits to make them testable
VLSI testing and design-for-testability in SystemVerilog: stuck-at fault models, serial fault simulation, an LFSR test-pattern generator and a 4-bit scan chain.
SystemVerilog/Python research prototype for reliability-aware runtime DFT scheduling in robotic SoCs, with fault injection and automated verification.
A .NET cinema ticket reservation system demonstrating a practical testing strategy.
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